The present invention relates to a high speed lock-up phase locked loop circuit, and more particularly to a high speed lock-up phase locked loop circuit capable of form switching between two states of a high speed response circuit enabling a high speed lock-up operation and a low speed response circuit realizing a low noise.
In Japanese laid-open patent publication No. 9-8655, it is disclosed that the high speed lock-up low noise phase locked loop circuit uses two phase comparators with different characteristics. FIG. 1 is a block diagram illustrative of a conventional high speed lock-up low noise phase locked loop circuit. This conventional high speed lock-up low noise phase locked loop circuit has a loop filter 3, a programmable divider 4, a voltage control oscillator 5 connected to the programmable divider 4 for sending the output from the voltage control oscillator 5 to the programmable divider 4, an overlap output phase comparator 6 connected to the programmable divider 4 for receiving both the output from the programmable divider 4 and a reference signal 1 externally inputted to compare the output from the programmable divider 4 with reference to the reference signal 1, a non-overlap output phase comparator 7 connected to the programmable divider 4 for receiving both the output from the programmable divider 4 and the reference signal 1 to compare the output from the programmable divider 4 with reference to the reference signal 1, a first charge pump circuit 8 connected to the overlap output phase comparator 6 for receiving the outputs from the overlap output phase comparator 6, and a second charge pump circuit 9 connected to the non-overlap output phase comparator 7 for receiving the outputs from the non-overlap output phase comparator 7. The above loop filter 3 are also connected to the output sides of the overlap output phase comparator 6 and the non-overlap output phase comparator 7 for receiving the individual outputs from the overlap output phase comparator 6 and the non-overlap output phase comparator 7. The voltage control oscillator 5 is also connected to the loop filter 3 for receiving the output from the loop filter 3. The output from the voltage control oscillator 5 is fetched as the output signal 2 as the above conventional high speed lock-up low noise phase locked loop circuit.
The following description ill focus on the operations of the above conventional high speed lock-up low noise phase locked loop circuit. The non-overlap output phase comparator 7 compares the output from the programmable divider 4 with reference to the reference signal 1 in phase so as to detect a phase difference of the output signal from the programmable divider 4 from the reference signal 1. If the detected phase difference of the output signal from the programmable divider 4 from the reference signal 1 is within a predetermined allowable range, the the non-overlap output phase comparator 7 is operated to output no phase difference signal about of the phase difference. The overlap output phase comparator 6 also compares the output from the programmable divider 4 with reference to the reference signal 1 in phase so as to detect the phase difference of the output signal from the programmable divider 4 from the reference signal 1. If the detected phase difference of the output signal from the programmable divider 4 from the reference signal 1 is within the predetermined allowable range, then the overlap output phase comparator 6 is operated to output no phase difference signal about of the phase difference.
For example, in an initial state of switching the frequency, the phase difference of the output signal from the programmable divider 4 from the reference signal 1 is likely to be large. If the phase difference is large or beyond the predetermined allowable range, then the overlap output phase comparator 6 is operated to output the phase difference signal which is transmitted to the first charge pump circuit 8, and also the non-overlap output phase comparator 7 is operated to output the phase difference signal which is also transmitted to the second charge pump circuit 9. The loop filter 3 is driven by the first and second charge pump circuits 8 and 9, whereby the high speed lock-up low noise phase locked loop circuit exhibits high speed performances.
After a predetermined time has been passed from the commencement of switching the frequency, the phase difference of the output signal from the programmable divider 4 from the reference signal 1 is likely to comes small to be within the predetermined allowable range. If the phase difference is large or beyond the predetermined allowable range, then the overlap output phase comparator 6 and the non-overlap output phase comparator 7 are operated to output no phase difference signals. The loop filter 3 is not driven by only the first charge pump circuit 8, whereby the high speed lock-up low noise phase locked loop circuit exhibits low speed and low noise performances.
The above high speed lock-up low noise phase locked loop circuit is switched between two different states of the high speed and low speed responsibilities by the two phase comparators.
The above high speed lock-up low noise phase locked loop circuit has a problem in providing the two phase comparators, which results in a large scale of the circuits.
The above high speed lock-up low noise phase locked loop circuit has another problem in a difficulty to charge or vary the predetermined allowable range which provides a critical range of whether or not the phase difference signals are outputted from the overlap output phase comparator 6 and the non-overlap output phase comparator 7. This difficulty to charge or vary the predetermined allowable range means it also difficult to adjust a critical value of switching the circuit performances between the high speed and low speed responses.
In the above circumstances, it had been required to develop a novel high speed lock-up phase locked loop circuit free from the above problems.